EE 363 Computer System Architecture I
- 1996-97 Catalog Data: 4 credits
- Concepts of modern computer architecture. Processor micro-arcitectures, hardwired vs. micro-programmed control, piplining and pipeline hazards, memory heirarchies, bus-based system architecture and memory mapping, hardware-software interface, and operating system concepts. Prerequisites: EE 265 and CS 273. Same as CS 363.
- Textbooks:
- Computer System Architecture, Third Edition, M. Morris Mano, Prentice Hall.
- Reference:
- TTL Logic Data Book, Texas Instruments.
- 8086/8088 User's Manual, Programmer's and Hardware Reference, Intel.
- Micro-Architecture, Version 2.0, A.K. Petersen, NMSU.
- Micro-Compiler, Version 2.0, A.K. Petersen, NMSU.
- Micro-Simulator, Version 2.0, A.K. Petersen, NMSU.
- Coordinator:
- A.K. Petersen, Instructor of Electrical and Computer Engineering.
- Goals:
- To study various aspects of computer system architectures: digital signals, combinational and sequential circuits; processor architectures at both the macro level (macroarchitecture, register transfer) and the micro level (microarchitecture, microcoding); system architectures, including peripheral devices, bus organizations, hierarchical memory organizations, and timing; and an introduction to RISC architecture and programming.
- In labs, students design software to handle interrupts and peripheral devices, while in class students design microcode implementations of a wide spectrum of macro-level assembly instructions (beyond just the Intel instruction repertoire).
- Prerequisites by topic:
- Combinational digital logic (EE 265).
- Assembly language programming and machine organization (CS 273).
- Topics:
- Fundamentals: Assembly Language Programming, Data Representation, IC Logic Functions, Register Transfer Notation, Basic Computer Organization. (6 classes).
- Processor Architecture: Processor Internal Organization, Microarchitecture, Microprogramming. (24 classes).
- RISC Architectures. (5 classes).
- I/O and Memory Organization: Local Bus Organization, Timing, Interfaces; System Bus Organization and Arbitration; Analysis of PC Design: the PC XT System Diagrams; Memory Hierarchy: Cache Memory, Segmented Virtual Memory. (10 classes).
- Computer Usage:
- Lecture: IBM 486 clones running a micro-compiler and GUI micro-architecure simulator.
- Lab: IBM 486 clones running MS-DOS with DEBUG, networked to Sun 4/80s running Unix with an AMD29000 assembler.
- Laboratory projects (including major items of equipment and instrumentation used):
- Design and debug a program which uses operating system calls and timing loops to cause the PC/XT speaker to sound a 440Hz tone for one second whenever a keyboard key is pressed.
- Hand translate from Pascal to assembly language a program to implement the Sieve of Erastosthenes method of computing prime numbers, and debug the program.
- Design a program to drive the PC/XT timer chip and speaker on the basis of a data structure representation of a musical tune so as to produce the tune as audio output.
- Design a software package to intercept keyboard interrupts by changing the interrupt vector table to divert the interrupt acknowledge to a user-supplied handler, and to generate an audio indication of the interrupt interception.
- Design and test an AMD29000 program which is equivalent to the program of Lab 2.
- ABET Category Content:
- Engineering science: 2 credits or 50%
- Engineering design: 2 credits or 50%
- Prepared by:
- A. K. Petersen
- Date: February 14, 1994
Maintained by eeoffice@nmsu.edu Last update 12-12-96